Image sensors, methods, and pixels with storage and transfer gates

ABSTRACT

An image sensor includes a pixel array with a plurality of pixels. A pixel includes a photodiode, a first transfer gate, a storage gate, and a second transfer gate. The first transfer gate is controllable to transfer charge from the photodiode to under the storage gate. The storage gate is connected to a readout circuit to allow the readout circuit to read out a voltage level of a potential at the storage gate. The second transfer gate is controllable to transfer charge from under the storage gate. A method includes controlling the first transfer gate to transfer charge from the photodiode to under the storage gate, reading out a voltage level of a potential at the storage gate using the readout circuit that is connected to the storage gate, and controlling the second transfer gate to drain charge from under the storage gate.

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

This application claims the benefit of U.S. Provisional App. Ser. No.61/285,457, entitled “Shutter Pixel with Floating Gate Storage andReadout and Image Sensors with Shutter Pixels,” filed Dec. 10, 2009, theentire contents of which are incorporated by reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the present invention relate generally to image sensors,pixels, and methods and, in specific embodiments, to a pixel having astructure allowing for charge storage and readout.

2. Related Art

Various types of image sensors and pixels are discussed in U.S. Pat. No.7,443,437, entitled “Image Sensor with a Gated Storage Node Linked toTransfer Gate,” which issued on Oct. 28, 2008, the entire contents ofwhich are incorporated by reference herein, and which is hereinafterreferred to as the '437 patent. In particular, FIG. 2 of the '437 patentillustrates a pixel with a photodiode, a shutter gate, and a transfergate. In that pixel, a barrier region and a storage node are implementedunder the shutter gate, with the barrier region under a portion of theshutter gate adjacent to the photodiode to create a barrier, and thestorage node under another portion of the shutter gate to create apotential well for storage. One of the drawbacks of such a pixelstructure might be a leakage of photoelectrons into the storage node,which is very close to a buried channel depleted area of the photodiode.

SUMMARY OF THE DISCLOSURE

A pixel in accordance with an embodiment of the present inventionincludes a photodiode, a first transfer gate, a storage gate, and asecond transfer gate. The first transfer gate is controllable totransfer charge from the photodiode to under the storage gate. Thestorage gate is connected to a readout circuit to allow the readoutcircuit to read out a voltage level of a potential at the storage gate.The second transfer gate is controllable to transfer charge from underthe storage gate.

In various embodiments, the storage gate is located between the firsttransfer gate and the second transfer gate. Also, in variousembodiments, the storage gate is charge coupled to the first transfergate and is charge coupled to the second transfer gate. In someembodiments, the readout circuit includes a source follower transistor.Also, in some embodiments, the storage gate is directly connected to agate of the source follower transistor. In further embodiments, thereadout circuit includes a read select transistor that is connectedbetween the source follower transistor and a readout line and that has agate connected to receive a row select signal.

In various embodiments, the pixel includes a drain diffusion to whichcharge is drainable from under the storage gate by the second transfergate. Also, in various embodiments, the pixel includes a resettransistor that is connected between a reset voltage source and thestorage gate and that has a gate connected to receive a reset controlsignal. In some embodiments, the pixel includes an anti-blooming gatefor draining charge from the photodiode into a drain diffusion. Also, insome embodiments, the anti-blooming gate is located on an opposite sideof the photodiode relative to the first transfer gate.

In various embodiments, the pixel includes a substrate on which is thefirst transfer gate, the storage gate, and the second transfer gate. Insome embodiments, the first transfer gate is connected to receive afirst transfer control signal and the second transfer gate is connectedto receive a second transfer control signal. Also, in some embodiments,the second transfer gate is located on an opposite side of the storagegate relative to the first transfer gate.

In various embodiments, the storage gate, the first transfer gate, andthe second transfer gate are polysilicon gates that are in a singlepolysilicon level. Also, in various embodiments, the pixel includes aseries of surface BF2 implants on a substrate. In such embodiments, onesurface BF2 implant is done as a blanket implant before Poly deposition,and it covers the area of the photodiode, the first and the secondtransfer gates, as well as the storage gate. A second BF2 implant isalso done before Poly deposition and it covers the photodiode and aportion of area under the first transfer gate. A third BF2 implant isdone after Poly formation and it covers the photodiode area only.

In various embodiments, the photodiode area is implanted with an arsenicimplant to form a buried photodiode. Further, in some embodiments, thepixel includes a blanket arsenic buried channel implant on a substrate,which is done before Poly deposition and which covers the areas of thephotodiode, the first and the second transfer gates, as well as thestorage gate area. Also, in some embodiments, the photodiode includes abackside boron implant to increase the charge capacity of thephotodiode.

In various embodiments, the pixel includes a standard Pwell implant orseries of Pwell implants covering the storage area to reduce the leakageof a photocurrent from the substrate into the area under the storagegate, thereby increasing the shutter efficiency. Another function ofPwell implants is to perform pixel-to-pixel isolation and crosstalkreduction.

In some embodiments, the blanket surface BF2 implant and the blanketarsenic implant are not implemented, thereby the storage gate performsas a surface channel storage. Also, in various embodiments, the pixelincludes a gap implant on both sides of the storage gate, between thestorage gate and the first transfer gate, and between the storage gateand the second transfer gate, where the gap implant includes arsenic orboron. The purpose of the gap implant is to reduce the potential barrierin the substrate between the gates.

A method in accordance with an embodiment of the present inventionincludes controlling a first transfer gate to transfer charge from aphotodiode to under a storage gate, reading out a voltage level of apotential at the storage gate using a readout circuit that is connectedto the storage gate, and controlling a second transfer gate to draincharge from under the storage gate. In various embodiments, the methodfurther includes controlling an anti-blooming gate to drain charge fromthe photodiode, where the anti-blooming gate is located on an oppositeside of the photodiode relative to the first transfer gate.

In various embodiments, charge transferred to under the storage gatefrom the photodiode is stored under the storage gate during the readingout of the voltage level of the potential at the storage gate. Also, invarious embodiments, the method includes reading out another voltagelevel of another potential at the storage gate using the readout circuitafter controlling the second transfer gate to drain charge from underthe storage gate. In some embodiments, charge from under the storagegate is transferred directly though a channel under the second transfergate to a drain diffusion during the controlling of the second transfergate to drain charge from under the storage gate. Also, in someembodiments, the method includes reading out another voltage level ofanother potential at another storage gate using the readout circuit.

An image sensor in accordance with an embodiment of the presentinvention includes a pixel array that has a plurality of pixels. Invarious embodiments, each pixel of the plurality of pixels includes aphotodiode, a storage gate, a first transfer gate controllable totransfer charge from the photodiode to under the storage gate, and asecond transfer gate controllable to transfer charge from under thestorage gate. Also, in various embodiments, each storage gate of eachpixel is connected to a corresponding readout circuit to allow thecorresponding readout circuit to read out a voltage level of a potentialat the storage gate. In some embodiments, the respective storage gatesof two or more of the plurality of pixels are directly connected to asame readout circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a pixel in accordance with an embodiment of thepresent invention;

FIG. 2 illustrates an image sensor in accordance with an embodiment ofthe present invention;

FIG. 3 illustrates a flowchart of a method in accordance with anembodiment of the present invention;

FIG. 4 illustrates a portion of a pixel in accordance with an embodimentof the present invention; and

FIG. 5 illustrates a circuit in accordance with an embodiment of thepresent invention with four pixels that share a readout circuit.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1 illustrates a pixel 7 in accordance with an embodiment of thepresent invention. The pixel 7 comprises a substrate 10, a photodiode(PD) 11, a first transfer gate 12, a storage gate 13, a second transfergate 14, an anti-blooming gate 15, a drain diffusion 51, a draindiffusion 52, a reset transistor 16, and a readout circuit 19. Thereadout circuit 19 comprises a source follower transistor (SF) 17 and aread select transistor 18. The readout circuit 19 is connected to areadout line 53 for outputting signals from the pixel 7. The photodiode11 is sensitive to light and can provide charge in response to light.

The first transfer gate 12 is connected to receive a first transfercontrol signal (TX), and the first transfer gate 12 is controllable bythe first transfer control signal TX to transfer charge from thephotodiode 11 to under the storage gate 13. The second transfer gate 14is connected to receive a second transfer control signal (TX2), and thesecond transfer gate 14 is controllable by the second transfer controlsignal TX2 to transfer charge from under the storage gate 13 to thedrain diffusion 52, such that charge is drainable from under the storagegate 13 to the drain diffusion 52 by operation of the second transfergate 14. The storage gate 13 is connected to the readout circuit 19 toallow the readout circuit 19 to read out a voltage level of a potentialat the storage gate 13. Thus, the storage gate 13 serves for both chargestorage and for allowing for a charge signal to be read out of the pixel7.

The second transfer gate 14 is located on an opposite side of thestorage gate 13 relative to the first transfer gate 12, such that thestorage gate 13 is located between the first transfer gate 12 and thesecond transfer gate 14. The storage gate 13 is charge coupled to thefirst transfer gate 12, and the storage gate 13 is also charge coupledto the second transfer gate 14. The anti-blooming gate 15 is located onan opposite side of the photodiode 11 relative to the first transfergate 12. The anti-blooming gate 15 is connected to receive ananti-blooming control signal (AB), and the anti-blooming gate 15 iscontrollable by the anti-blooming control signal AB to allow for chargeto be drained from the photodiode 11 to the drain diffusion 51.

A first terminal of the reset transistor 16 is connected to a resetvoltage source that provides a reset voltage (Vrst). A gate of the resettransistor 16 is connected to receive a reset control signal (RST). Asecond terminal of the reset transistor 16 is connected to the storagegate 13 and to a gate of the source follower transistor 17. Thus, thereset transistor 16 is connected between the reset voltage source thatprovides the reset voltage Vrst and the storage gate 13. The gate of thesource follower transistor 17 is connected to the storage gate 13 and tothe second terminal of the reset transistor 16. In the embodiment shownin FIG. 1, the storage gate 13 is directly connected to the gate of thesource follower transistor 17. A first terminal of the source followertransistor 17 is connected to a voltage source that supplies a voltage(Vdd).

A second terminal of the source follower transistor 17 is connected to afirst terminal of the read select transistor 18. A gate of the readselect transistor 18 is connected to receive a row select signal (ROW).A second terminal of the read select transistor 18 is connected to thereadout line 53 for providing a pixel output signal (pout) for the pixel7 on the readout line 53. Thus, the read select transistor 18 isconnected between the source follower transistor 17 and the readout line53. In the embodiment shown in FIG. 1, the readout circuit 19 includesthe source follower transistor 17 and the read select transistor 18 forreading out a signal based on a voltage level of a potential at thestorage gate 13. It should be appreciated that, in various otherembodiments, the readout circuit 19 may have various other circuitstructures that still provide for reading out a signal based on avoltage level of a potential at the storage gate 13. In variousembodiments, the pixel 7 is used as a shutter pixel.

FIG. 2 illustrates an architecture of an image sensor 100 in accordancewith an embodiment of the present invention. The image sensor 100comprises a pixel array 84, a row driver 80, an analog-to-digitalconversion (ADC) controller 90, and a plurality of column readoutcircuits 92. The pixel array 84 comprises pixels 7 that are arranged inrows and columns, and each of the pixels 7 has a same structure as thepixel 7 shown in FIG. 1. With reference to FIGS. 1 and 2, the row driver80 supplies control signals to the pixels 7 in the pixel array 84 tocontrol an operation of the pixels 7. Pixels 7 that are in a same row ofthe pixel array 84 share common row control signals from the row driver80.

For example, pixels 7 in a first row of the pixel array 84 share commonrow control lines 81 ₁ for receiving control signals from the row driver80. The row control lines 81 ₁ may include signal lines for the firsttransfer control signal TX, the second transfer control signal TX2, theanti-blooming control signal AB, the reset control signal RST, and therow select signal ROW for the pixels 7 in the first row of the pixelarray 84, and the row driver 80 may be configured to generate each ofthose signals. Similarly, pixels 7 in a second row of the pixel array 84share common row control lines 81 ₂ for receiving control signals fromthe row driver 80, and pixels 7 in an h^(th) row of the pixel array 84share common row control lines 81 _(h) for receiving control signalsfrom the row driver 80.

Pixels 7 that are in a same column of the pixel array 84 may share acommon readout line to provide output. For example, pixels 7 in a firstcolumn of the pixel array 84 share a readout line 53 _(k), pixels 7 in asecond column of the pixel array 84 share a readout line 53 ₂, andpixels 7 in an m^(th) column of the pixel array 84 share a readout line53 _(m). In various embodiments, the row driver 80 controls the pixels 7to provide output row by row. Also, in various embodiments, the rowdriver 80 controls the pixels 7 to output signals representing chargestored at the pixels 7 for an image capture operation and to outputreference signals after charge has been drained in the pixels 7.

In various embodiments, each column readout circuit 92 is connected toreceive analog signals from a corresponding readout line from the pixelarray 84, and is configured to provide digital output on a correspondingoutput line. For example, the column readout circuit 92 for the firstcolumn is connected to the readout line 53 ₁ for receiving input, and isconnected to an output line 94 ₁ for providing output. Similarly, thecolumn readout circuit 92 for the second column is connected to thecolumn readout line 53 ₂ for receiving input, and is connected to anoutput line 94 ₂ for providing output, and the column readout circuit 92for the m^(th) column is connected to the column readout line 53 _(m),for receiving input, and is connected to an output line 94 _(m), forproviding output. The ADC controller 90 is configured to provide controlsignals to the plurality of column readout circuits 92 over one or morecontrol lines 93.

FIG. 3 illustrates a flowchart of a method 110 performed by a pixel,such as the pixel 7 of FIG. 1, in accordance with an embodiment of thepresent invention. With reference to FIGS. 1 and 3, the method 110starts with an exposure mode (which may also be called a photo-chargecharge integration mode) at step 111 in which charge is accumulated atthe photodiode 11 in response to light. In the exposure mode, the firsttransfer control signal TX to the first transfer gate 12 is controlledto be a LOW voltage so that photoelectrons can be contained in thephotodiode 11. During the exposure mode, photogenerated carriers diffuseor drift from the substrate 10 to the photodiode 11, which is a buriedphotodiode, and charge accumulates at the photodiode 11. Following theexposure mode, the method 110 then continues to a transfer mode in step112.

In the transfer mode in step 112, the first transfer gate 12 iscontrolled to transfer charge from the photodiode 11 to under thestorage gate 13. For the transfer mode, the first transfer controlsignal TX to the first transfer gate 12 is controlled to be a HIGHvoltage, and the second transfer control signal TX2 to the secondtransfer gate 14 is controlled to be a LOW voltage. Also, during thetransfer mode, a HIGH voltage is applied to the storage gate 13 bycontrolling the reset control signal RST that is applied to the gate ofthe reset transistor 16 to be a HIGH voltage, such that the HIGH voltageof Vrst goes to the storage gate 13. In various embodiments, thetransfer mode may be performed globally at a same time on all pixels inan entire pixel array that includes the pixel 7. During the transfermode (which may also be called a transfer phase), charges from thephotodiode 11 flow through a channel under the first transfer gate 12 tounder the storage gate 13, such that charge that was accumulated at thephotodiode 11 during the exposure mode is stored under the storage gate13. The transfer mode is ended by controlling the first transfer controlsignal TX that is applied to the first transfer gate 12 to be a LOWvoltage.

After the transfer mode, the method 110 continues to step 113 to start areadout from the pixel 7. The reset control signal RST that is appliedto the gate of the reset transistor 16 is controlled to be a LOW voltageso as to turn off the reset transistor 16. Once the reset transistor 16has been turned off, the storage gate 13 becomes a floating gate. Avoltage level of a potential at the storage gate 13 is then read outusing the readout circuit 19 that is connected to the storage gate 13.To perform the read out, the row select signal ROW that is applied tothe gate of the read select transistor 18 is controlled to be a HIGHvoltage, which causes a signal representing the voltage level of thepotential at the storage gate 13 to be output from the pixel 7 on thereadout line 53. Such an output signal allows for a column storage (notshown), which may be part of a corresponding column readout circuit 92(refer to FIG. 2), to measure and store the voltage level correspondingto the potential at the storage gate 13 when the storage gate 13 is“with charge.” The signal is read out through the source followertransistor 17 and the read select transistor 18 loaded onto a sourcefollower current sink (not shown), where the source follower currentsink may also be part of the corresponding column readout circuit 92(refer to FIG. 2). The method 110 then continues to step 114.

In step 114, the second transfer gate 14 is controlled to drain chargefrom under the storage gate 13. The second transfer control signal TX2that is applied to the second transfer gate 14 is controlled to be aHIGH voltage. Charges from under the storage gate 13 then flow through achannel under the second transfer gate 14 and are drained into the draindiffusion 52 that is connected to Vdd. In the pixel 7, charge from underthe storage gate 13 is transferred directly through a channel under thesecond transfer gate 14 to the drain diffusion 52 when the HIGH voltageis applied to the second transfer gate 14.

The method 110 then continues to step 115, in which another voltagelevel of another potential at the storage gate 13 is read out using thereadout circuit 19. The row select signal ROW that is applied to thegate of the read select transistor 18 is controlled to be a HIGHvoltage, which causes a signal representing the voltage level of thepotential at the storage gate 13 to be output from the pixel 7 on thereadout line 53. Such an output signal allows for a column storage (notshown), which may be part of the corresponding column readout circuit 92(refer to FIG. 2), to measure and store the voltage level correspondingto the potential at the storage gate 13 after charge has been drainedfrom the storage gate 13. The output signal can thus serve as areference signal for a voltage level of a potential at the storage gate13 when the storage gate 13 supposedly has “no charge.”

The corresponding column readout circuit 92 (refer to FIG. 2) may thendetermine a difference between the previously stored output signalrepresenting the “with charge” state and the reference signalrepresenting the “no charge” state, and may use the difference togenerate a digital value for the pixel output. The difference does nothave kTC noise of a capacitance of the storage gate 13, so thedifference represents a true correlated double sampling and features lownoise. The method 110 may then be repeated to capture additional images.

In various embodiments of the method 110, after the transfer of chargeto under the storage gate 13 in step 112, the charge transferred tounder the storage gate 13 from the photodiode 11 is stored under thestorage gate 13 during the reading out of the voltage level in step 113.In some embodiments, the voltage at the storage gate 13 may be reducedin a storage mode to reduce dark current and to squeeze out excessivecharge. In some embodiments, the anti-blooming gate 15 may be controlledto drain excessive charge from the photodiode 11 if desired into thedrain diffusion 51 that is connected to Vdd. With reference to FIGS. 1,2, and 3, in various embodiments, the readout from the pixels 7 in thepixel array 84 may be performed row by row using steps 113, 114, and 115of the method 110 after all charges are stored under the storage gate 13of each pixel 7 over the entire pixel array 84, such that the voltagelevels for charges can be read out row by row. In various embodiments,to perform readout for a selected row, a HIGH voltage would be providedto the row select signal ROW for the row.

FIG. 4 illustrates a portion 70 of the pixel 7 of FIG. 1 in accordancewith an embodiment of the present invention. In various embodiments, thesubstrate 10 comprises a lightly doped P-type epi-layer on a P+substrate. Exemplary implants in the substrate 10 are shown in FIG. 4,and the exemplary implants are as follows: (i) a surface blanket BF2pinned implant 31 before polysilicon; (ii) a pwell aligned VTcompensation BF2 pinned implant 32 before polysilicon; (iii) aphotodiode BF2 pinned implant 33 at lightly doped drain (LDD) stage;(iv) a blanket arsenic (AS) buried channel implant 34 beforepolysilicon; (v) a photodiode AS implant 35 at LDD stage; and (vi) abackside boron implant 36 at LDD stage. In various embodiments, thephotodiode 11 is implemented as a pinned photodiode with a surface BF2implant and a buried AS75 implant.

In various embodiments, the first transfer gate 12, the storage gate 13,the second transfer gate 14, and the anti-blooming gate 15 are formed onthe substrate 10. Also, in various embodiments, the first transfer gate12, the storage gate 13, and the second transfer gate 14 are polysilicongates that are implemented in a single polysilicon level with minimumgap between the polysilicon gates. The portion 70 of the pixel includesseparate storage and transfer gates, where the storage gate 13 isdistinct from the first transfer gate 12 and is distinct from the secondtransfer gate 14. The storage gate 13 is charge coupled to the firsttransfer gate 12 and is also charge coupled to the second transfer gate14. In some embodiments, a gap implant 57 is provided into gaps 58, 59between the storage gate 13 and the first transfer gate 12, and betweenthe storage gate 13 and the second transfer gate 14. The gap implant 57may be arsenic if the storage gate 13 is a surface channel storage gate,and may be arsenic or boron if the storage gate 13 is a buried channelstorage gate. The purpose of the gap implant 57 is to reduce a potentialbarrier in the substrate 10 between the gates, and it fixesimperfections of other implants in the gap area. The gap implant 57 isimplanted from the top of the structure down into the substrate 10, andthe polysilicon gates serve as a mask so that the gap implant only getsinto and through the gaps 58, 59.

In various embodiments, the surface blanket BF2 pinned implant 31 isdone as a blanket implant before Poly deposition, and it covers an areaof the photodiode 11, the first transfer gate 12, the storage gate 13,the second transfer gate 14, and the anti-blooming gate 15. Thus, invarious embodiments, the surface blanket BF2 pinned implant 31 isimplemented on the substrate 10 before polysilicon and covers areas ofthe first transfer gate 12, the storage gate 13, and the second transfergate 14. Also, in various embodiments, the photodiode 11 includes aportion of the surface blanket BF2 pinned implant 31.

In various embodiments, the pwell aligned VT compensation BF2 pinnedimplant 32 is also done before Poly deposition and it covers thephotodiode 11, a portion of area under the first transfer gate 12, and aportion of area under the anti-blooming gate 15. In various embodiments,the photodiode BF2 pinned implant 33 is done after Poly formation and itcovers an area of the photodiode 11 only. The pwell aligned VTcompensation BF2 pinned implant 32 overlaps part of the surface blanketBF2 pinned implant 31. The photodiode BF2 pinned implant 33 overlapspart of the pwell aligned VT compensation BF2 pinned implant 32 and partof the surface blanket BF2 pinned implant 31. The three BF2 implants maybe done one after another, so that the doses of the implants add in theoverlap places which have already been implanted. In FIG. 4, the surfaceblanket BF2 pinned implant 31, the pwell aligned VT compensation BF2pinned implant 32, and the photodiode BF2 pinned implant 33 are shown alittle staggered from each other in the depth direction so that each ofthe implants is visible, but it should be appreciated that in variousembodiments each of those implants starts at the surface of thesubstrate 10 and has approximately a same depth.

The photodiode area is implanted with arsenic implant to form a buriedphotodiode. In various embodiments, the portion 70 of the pixel includesthe blanket arsenic buried channel implant 34 on the substrate 10, whichis done before Poly deposition and which covers the areas of thephotodiode 11, the first transfer gate 12, the storage gate 13, thesecond transfer gate 14, and the anti-blooming gate 15. Thus, in variousembodiments, the photodiode 11 includes a portion of the blanket arsenicburied channel implant 34. The photodiode AS implant 35 overlaps theblanket arsenic buried channel implant 34 in the area of the photodiode11, and the doses of the implants add in the overlap. In FIG. 4, theblanket arsenic buried channel implant 34 and the photodiode AS implant35 are shown a little staggered from each other in the depth directionso that each of the implants is visible, but it should be appreciatedthat in various embodiments each of those implants starts atapproximately a same depth and continues to approximately a same depth.In some embodiments, the photodiode 11 includes the backside boronimplant 36 to increase a charge capacity of the photodiode 11.

In various embodiments, the portion 70 of the pixel includes a Pwellimplant or series of Pwell implants covering the storage area to reducethe leakage of a photocurrent from the substrate 10 into the area underthe storage gate 13, thereby increasing the shutter efficiency. Anotherfunction of Pwell implants is to perform pixel-to-pixel isolation andcrosstalk reduction. In various embodiments, each Pwell implant is acombination of Boron and BF2 implants of various energy and dose. Insome embodiments, the surface blanket BF2 pinned implant 31 and theblanket arsenic buried channel implant 34 are not implemented, therebythe storage gate 13 performs as a surface channel storage. In someembodiments, the storage gate 13 is implemented as a buried channeldevice, with a surface boron implant and a buried arsenic or phosphorousimplant.

FIG. 5 illustrates a circuit 20 in accordance with an embodiment of thepresent invention. The circuit 20 includes four pixels 21 ₁, 21 ₂, 21 ₃,21 ₄, with structures similar to the pixel 7 (refer to FIG. 1), but thefour pixels 21 ₁, 21 ₂, 21 ₃, 21 ₄, share a common reset transistor 22and a common readout circuit 27. Thus, the four pixels 21 ₁, 21 ₂, 21 ₃,21 ₄, share pixel readout elements. Each pixel 21 _(i) comprises aphotodiode 11 _(i), a first transfer gate 12 _(i), a storage gate 13_(i), a second transfer gate 14 _(i), and an anti-blooming gate 15 _(i)(i=1, 2, 3, 4). The readout circuit 27 comprises a source followertransistor 23 and a read select transistor 24. The readout circuit 27 isconnected to a readout line 25 to provide output from the pixels.

A first terminal of the reset transistor 22 is connected to a resetvoltage source that provides a reset voltage Vrst. A gate of the resettransistor 22 is connected to receive a reset control signal RST. Asecond terminal of the reset transistor 22 is connected to each of thestorage gates 13 ₁, 13 ₂, 13 ₃, 13 ₄, and to a gate of the sourcefollower transistor 23. The gate of the source follower transistor 23 isconnected to each of the storage gates 13 ₁, 13 ₂, 13 ₃, 13 ₄, and tothe second terminal of the reset transistor 22. A first terminal of thesource follower transistor 23 is connected to a voltage source thatsupplies a voltage Vdd. A second terminal of the source followertransistor 23 is connected to a first terminal of the read selecttransistor 24. A gate of the read select transistor 24 is connected toreceive a row select signal ROW. A second terminal of the read selecttransistor 24 is connected to the readout line 25.

Each of the pixels is connected to receive a first transfer controlsignal TX, a corresponding second transfer control signal TX2 _(i) (i=1,2, 3, 4), and an anti-blooming control signal AB. The pixels 21 ₁, 21 ₂,21 ₃, 21 ₄, are read out in order, and the readout operations for eachof the pixels 21 ₁, 21 ₂, 21 ₃, 21 ₄, is similar to the readoutdescribed for the method 110 (refer to FIG. 3). The storages under thestorage gates 13 ₁, 13 ₂, 13 ₃, 13 ₄, are emptied one by one using fourseparate controls TX2 ₁, TX2 ₂, TX2 ₃, TX2 ₄, to the respective secondtransfer gates 14 ₁, 14 ₂, 14 ₃, 14 ₄.

In various embodiments, the operation of the circuit 20 is as follows.Photocharge is accumulated in each of the photodiodes 11 ₁, 11 ₂, 11 ₃,11 ₄. An exposure time is controlled with the anti-blooming gates 15 ₁,15 ₂, 15 ₃, 15 ₄. The exposure starts with controlling the anti-bloomingcontrol signal AB to be LOW. When the anti-blooming control signal AB iscontrolled to be HIGH, photodiode charges are drained out through therespective anti-blooming gates 15 ₁, 15 ₂, 15 ₃, 15 ₄. The exposure endswith a transfer of charge from all of the photodiodes 11 ₁, 11 ₂, 11 ₃,11 ₄ to the corresponding storage gates 13 ₁, 13 ₂, 13 ₃, 13 ₄ throughglobal transfer by controlling the first transfer control signal TX toapply HIGH to all first transfer gates 12 ₁, 12 ₂, 12 ₃, 12 ₄. Thestorage gates 13 ₁, 13 ₂, 13 ₃, 13 ₄ during the transfer are kept at aDC voltage through connected reset transistor 22 by controlling thereset control signal RST to be HIGH. The charge from each of thephotodiodes 11 ₁, 11 ₂, 11 ₃, 11 ₄ is stored under the respectivestorage gates 13 ₁, 13 ₂, 13 ₃, 13 ₄.

The readout is done in the group of four pixels 21 ₁, 21 ₂, 21 ₃, 21 ₄one-by-one. The combined storage gate of the four pixels 21 ₁, 21 ₂, 21₃, 21 ₄ is reset by controlling the reset control signal RST to be HIGHand then is left floating by controlling the reset control signal RST tobe LOW. The floating potential is then measured using the readoutcircuit 27. The charge from the first pixel 21 ₁ is then dumped to thedrain by controlling the corresponding second transfer control signalTX2 ₁ applied to the second transfer gate 14 ₁ to be HIGH. A secondpotential is then measured using the readout circuit 27, whichcorresponds to the charge gone.

The combined storage gate of the four pixels 21 ₁, 21 ₂, 21 ₃, 21 ₄ isreset again by controlling the reset control signal RST to be HIGH andthen is left floating by controlling the reset control signal RST to beLOW. The floating potential of the floating combined gate is thenmeasured using the readout circuit 27. The charge from the second pixel21 ₂ is then dumped to the drain by controlling the corresponding secondtransfer control signal TX2 ₂ applied to the second transfer gate 14 ₂to be HIGH. A second potential is then measured using the readoutcircuit 27, which corresponds to the charge left from under the storagegate 13 ₂. The readout is then repeated for the pixel 21 ₃ and the pixel21 ₄, so that all four charges are read out.

The embodiment shown in FIG. 5 is a 4-share architecture in which thepixel readout elements are shared by four neighboring pixels. In variousother embodiments, different numbers of pixels may share pixel readoutelements. For example, a circuit may be constructed in a 2-sharearchitecture in which pixel readout elements are shared by twoneighboring pixels. In various embodiments, an image sensor includes apixel array with pixels in 2-share or 4-share architectures, such thatthe respective storage gates of two or more of the pixels in the pixelarray are directly connected to a same readout circuit. In suchembodiments, a voltage level of a potential at a storage gate of a firstpixel may be read out using a readout circuit that is connected to thestorage gate of the first pixel, and the same readout circuit may alsobe used to read out another voltage level of another potential at astorage gate of a second pixel.

The embodiments disclosed herein are to be considered in all respects asillustrative, and not restrictive of the invention. The presentinvention is in no way limited to the embodiments described above.Various modifications and changes may be made to the embodiments withoutdeparting from the spirit and scope of the invention. Variousmodifications and changes that come within the meaning and range ofequivalency of the claims are intended to be within the scope of theinvention.

What is claimed is:
 1. A pixel, comprising: a readout circuit; a storagegate that is connected to the readout circuit to allow the readoutcircuit to read out a voltage level of a potential at the storage gate;a first transfer gate controllable to transfer charge from a photodiodeto under the storage gate; a second transfer gate controllable totransfer charge from under the storage gate; and a drain diffusion towhich charge is drainable from under the storage gate by the secondtransfer gate, the drain diffusion directly connected to a voltagesource that supplies a constant voltage.
 2. A pixel, comprising: astorage gate that is connected to a readout circuit to allow the readoutcircuit to read out a voltage level of a potential at the storage gate;a first transfer gate controllable to transfer charge from a photodiodeto under the storage gate; a second transfer gate controllable totransfer charge from under the storage gate; and a reset transistor thatis connected between a reset voltage source and the storage gate andthat has a gate connected to receive a reset control signal.
 3. Thepixel of claim 2, further comprising an anti-blooming gate for drainingcharge from the photodiode into a drain diffusion, the anti-bloominggate located on an opposite side of the photodiode relative to the firsttransfer gate.
 4. The pixel of claim 2, further comprising a substrateon which is the first transfer gate, the storage gate, and the secondtransfer gate.
 5. The pixel of claim 2, wherein the storage gate, thefirst transfer gate, and the second transfer gate are polysilicon gatesthat are in a single polysilicon level.
 6. The pixel of claim 2, thefirst transfer gate connected to receive a first transfer control signaland the second transfer gate connected to receive a second transfercontrol signal.
 7. A pixel, comprising: a storage gate that is connectedto a readout circuit to allow the readout circuit to read out a voltagelevel of a potential at the storage gate; a first transfer gatecontrollable to transfer charge from a photodiode to under the storagegate; a second transfer gate controllable to transfer charge from underthe storage gate; and a gap implant between the storage gate and thefirst transfer gate and between the storage gate and the second transfergate, the gap implant comprising arsenic or boron.
 8. A pixel,comprising: a storage gate that is connected to a readout circuit toallow the readout circuit to read out a voltage level of a potential atthe storage gate; a first transfer gate controllable to transfer chargefrom a photodiode to under the storage gate; a second transfer gatecontrollable to transfer charge from under the storage gate; and asurface blanket BF2 implant on a substrate implemented beforepolysilicon and covering areas of the first transfer gate, the storagegate, and the second transfer gate.
 9. The pixel of claim 8, wherein thephotodiode includes a portion of the surface blanket BF2 implant.
 10. Apixel, comprising: a storage gate that is connected to a readout circuitto allow the readout circuit to read out a voltage level of a potentialat the storage gate; a first transfer gate controllable to transfercharge from a photodiode to under the storage gate; a second transfergate controllable to transfer charge from under the storage gate; and ablanket arsenic buried channel implant implemented before polysiliconand covering areas of the first transfer gate, the storage gate, and thesecond transfer gate.
 11. The pixel of claim 10, wherein the photodiodeincludes a portion of the blanket arsenic buried channel implant.
 12. Amethod, comprising: controlling a first transfer gate to transfer chargefrom a photodiode to under a storage gate; reading out a voltage levelof a potential at the storage gate using a readout circuit that isconnected to the storage gate; controlling a second transfer gate todrain charge from under the storage gate; and reading out anothervoltage level of another potential at the storage gate using the readoutcircuit after said controlling the second transfer gate to drain chargefrom under the storage gate and before controlling the first transfergate again to transfer other charge from the photodiode to under thestorage gate.
 13. The method of claim 12, the second transfer gatelocated on an opposite side of the storage gate relative to the firsttransfer gate.
 14. The method of claim 12, further comprisingcontrolling an anti-blooming gate to drain charge from the photodiode,the anti-blooming gate located on an opposite side of the photodioderelative to the first transfer gate.
 15. The method of claim 12, whereincharge transferred to under the storage gate from the photodiode isstored under the storage gate during said reading out of the voltagelevel of the potential at the storage gate.
 16. The method of claim 12,further comprising generating a digital value based on a differencebetween said voltage level and said another voltage level.
 17. Themethod of claim 12, wherein charge from under the storage gate istransferred directly though a channel under the second transfer gate toa drain diffusion during said controlling the second transfer gate todrain charge from under the storage gate; and wherein the draindiffusion is directly connected to a voltage source that supplies aconstant voltage.
 18. The method of claim 12, wherein the readoutcircuit reads out voltage levels from a first pixel, and the readoutcircuit also reads out voltage levels from a second pixel that is in adifferent row and a different column of a pixel array than a row andcolumn of the first pixel.
 19. An image sensor, comprising: a pixelarray comprising a plurality of pixels, each pixel of the plurality ofpixels comprising a photodiode, a storage gate, a readout circuit, afirst transfer gate controllable to transfer charge from the photodiodeto under the storage gate, and a second transfer gate controllable totransfer charge from under the storage gate; each storage gate of eachpixel connected to the readout circuit of the pixel to allow the readoutcircuit of the pixel to read out a voltage level of a potential at thestorage gate wherein each pixel of the plurality of pixels furthercomprising a drain diffusion that is directly connected to a voltagesource that supplies a constant voltage and to which charge is drainablefrom under the storage gate of the pixel by the second transfer gate ofthe pixel.
 20. A method, comprising: controlling a first transfer gateto transfer charge from a photodiode to under a storage gate; readingout a voltage level of a potential at the storage gate using a readoutcircuit that is connected to the storage gate; controlling a secondtransfer gate to drain charge from under the storage gate; andcontrolling a reset control signal that is applied to a gate of a resettransistor in order to reset the storage gate prior to said reading outthe voltage level of the potential at the storage gate.
 21. A method,comprising: controlling a first transfer gate to transfer charge from aphotodiode to under a storage gate; reading out a voltage level of apotential at the storage gate using a readout circuit that is connectedto the storage gate; controlling a second transfer gate to drain chargefrom under the storage gate; reading out another voltage level ofanother potential at the storage gate using the readout circuit aftersaid controlling the second transfer gate to drain charge from under thestorage gate; controlling a reset control signal that is applied to agate of a reset transistor in order to reset the storage gate after saidreading out of said another voltage level; and reading out a particularvoltage level of a particular potential at the storage gate using thereadout circuit after said controlling the reset control signal that isapplied to the gate of the reset transistor.
 22. The method of claim 21,further comprising controlling the second transfer gate to drain chargefrom under the storage gate after said reading out the particularvoltage level of the particular potential at the storage gate, and thenreading out a specific voltage level of a specific potential at thestorage gate using the readout circuit.